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TDA8933B
Class D audio amplifier
Rev. 01 -- 23 October 2008 Preliminary data sheet
1. General description
The TDA8933B is a high-efficiency class D amplifier with low power dissipation. The continuous time output power is 2 x 10 W in a stereo half-bridge application (RL = 8 ) or 1 x 20 W in a mono full-bridge application (RL =16 ). Due to the low power dissipation the device can be used without any external heat sink when playing music. Due to the implementation of Thermal Foldback (TF) the device remains operating with considerable music output power without the need for an external heat sink, even for high supply voltages and/or lower load impedances. The device has two full differential inputs driving two independent outputs. It can be used in a mono full-bridge configuration (Bridge-Tied Load (BTL)) or as stereo half-bridge configuration (Single-Ended (SE)).
2. Features
Operating voltage from 10 V to 36 V asymmetrical or 5 V to 18 V symmetrical Mono bridge-tied load (full-bridge) or stereo single-ended (half-bridge) application Application without heat sink using thermally enhanced small outline package High efficiency and low-power dissipation Thermal foldback to avoid audio holes Current limiting to avoid audio holes Full short circuit proof across load and to supply lines (using advanced current protection) I Internal or external oscillator (master-slave setting) that can be switched I No pop noise I Full differential inputs I I I I I I I
3. Applications
I I I I I I Flat-panel television sets Flat-panel monitor sets Multimedia systems Wireless speakers Mini/micro systems Home sound sets
NXP Semiconductors
TDA8933B
Class D audio amplifier
4. Quick reference data
Table 1. Quick reference data General; Vp = 25 V, fosc = 320 kHz, Tamb = 25 C unless specified otherwise Symbol Parameter VP IP Iq(tot) supply voltage supply current total quiescent current RMS output power Conditions asymmetrical supply Sleep mode Operating mode; no load; no snubbers or filter connected Min 10 Typ 25 0.6 40 Max 36 1.0 50 Unit V mA mA
Stereo SE channel; Rs < 0.1 [1] Po(RMS) continuous time output power per channel[2] RL = 4 ; VP = 17 V THD+N = 10 %, fi = 1 kHz RL = 8 ; VP = 25 V THD+N = 10 %, fi = 1 kHz Mono BTL channel; Rs < 0.1 [1] Po(RMS) RMS output power continuous time output power[2] RL = 8 ; VP = 17 V THD+N = 10 %, fi = 1 kHz RL = 16 ; VP = 25 V THD+N = 10 %, fi = 1 kHz
[1] [2]
7.5 9.3
8.5 10.3
-
W W
15.4 18.9
17.1 20.6
-
W W
Rs is the total series resistance of an inductor and an ESR single-ended capacitor in the application. Output power is measured indirectly, based on RDSon measurement.
5. Ordering information
Table 2. Ordering information Package Name TDA8933BTW Description Version SOT549-1 HTSSOP32 plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad Type number
TDA8933B_1
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Preliminary data sheet
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NXP Semiconductors
TDA8933B
Class D audio amplifier
6. Block diagram
OSCREF OSCIO VDDA 8 28 OSCILLATOR DRIVER HIGH VSSD PWM MODULATOR CTRL DRIVER LOW 26 29 27 BOOT1 VDDP1 OUT1 VSSP1
10
31
IN1P
2
IN1N INREF IN2P
3 12 15 PWM MODULATOR 14 PROTECTIONS: OVP, OCP, OTP, UVP, TF, WP MANAGER
21 20 DRIVER HIGH CTRL DRIVER LOW 23 22
BOOT2 VDDP2 OUT2 VSSP2
IN2N
VDDA STABILIZER 11 V 25 STAB1
DIAG
4 VDDA
VSSP1 24
STABILIZER 11 V CGND 7 VSSP2
STAB2
POWERUP
6
REGULATOR 5 V MODE VSSD
18
DREF
ENGAGE
5 VDDA 11 HVPREF
30
HVP1
TEST
13
TDA8933BTW
VSSA
19
HVP2
HALF SUPPLY VOLTAGE 9 1, 16, 17, 32
010aaa455
VSSA
VSSD(HW)
Fig 1.
Block diagram
TDA8933B_1
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TDA8933B
Class D audio amplifier
7. Pinning information
7.1 Pinning
VSSD(HW) IN1P IN1N DIAG ENGAGE POWERUP CGND VDDA VSSA
1 2 3 4 5 6 7 8 9
32 VSSD(HW) 31 OSCIO 30 HVP1 29 VDDP1 28 BOOT1 27 OUT1 26 VSSP1 25 STAB1 24 STAB2 23 VSSP2 22 OUT2 21 BOOT2 20 VDDP2 19 HVP2 18 DREF 17 VSSD(HW)
010aaa456
TDA8933BTW
OSCREF 10 HVPREF 11 INREF 12 TEST 13 IN2N 14 IN2P 15 VSSD(HW) 16
Fig 2.
Pin configuration diagram (HTSSOP32 package)
7.2 Pin description
Table 3. Symbol VSSD(HW) IN1P IN1N DIAG ENGAGE POWERUP CGND VDDA VSSA OSCREF HVPREF INREF TEST IN2N IN2P VSSD(HW) VSSD(HW) DREF
TDA8933B_1
Pinning description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description negative digital supply voltage and handle wafer connection positive audio input for channel 1 negative audio input for channel 1 diagnostic output; open-drain engage input to switch between Mute mode and Operating mode power-up input to switch between Sleep mode and Mute mode control ground; reference for POWERUP, ENGAGE and DIAG positive analog supply voltage negative analog supply voltage input internal oscillator setting (only master setting) decoupling of internal half supply voltage reference decoupling for input reference voltage test signal input; for testing purpose only negative audio input for channel 2 positive audio input for channel 2 negative digital supply voltage and handle wafer connection negative digital supply voltage and handle wafer connection decoupling of internal (reference) 5 V regulator for logic supply
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TDA8933B
Class D audio amplifier
Pinning description ...continued Pin 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Description half supply output voltage 2 for charging single-ended capacitor for channel 2 positive power supply voltage for channel 2 bootstrap high-side driver channel 2 Pulse Width Modulated (PWM) output channel 2 negative power supply voltage for channel 2 decoupling of internal 11 V regulator for channel 2 drivers decoupling of internal 11 V regulator for channel 1 drivers negative power supply voltage for channel 1 PWM output channel 1 bootstrap high-side driver for channel 1 positive power supply voltage for channel 1 half supply output voltage 1 for charging single-ended capacitor for channel 1 oscillator input in slave configuration or oscillator output in master configuration negative digital supply voltage and handle wafer connection
Table 3. Symbol HVP2 VDDP2 BOOT2 OUT2 VSSP2 STAB2 STAB1 VSSP1 OUT1 BOOT1 VDDP1 HVP1 OSCIO VSSD(HW)
Exposed die pad[1]
[1]
The exposed die pad has to be connected to VSSD(HW).
8. Functional description
8.1 General
The TDA8933B is a mono full-bridge or stereo half-bridge audio power amplifier using class D technology. The audio input signal is converted into a PWM signal via an analog input stage and a PWM modulator. To enable the output power Diffusion Metal Oxide Semiconductor (DMOS) transistors to be driven, this digital PWM signal is applied to a control and handshake block and driver circuits for both the high side and low side. A 2nd-order low-pass filter in the application converts the PWM signal to an analog audio signal across the loudspeakers. The TDA8933B contains two independent half bridges with full differential input stages. The loudspeakers can be connected in the following configurations:
* Mono full-bridge: Bridge-Tied Load (BTL) * Stereo half-bridge: Single-Ended (SE)
The TDA8933B contains circuits common to both channels such as the oscillator, all reference sources, the mode functionality and a digital timing manager. The following protections are built-in: thermal foldback and overtemperature, current and voltage protections.
TDA8933B_1
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Preliminary data sheet
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NXP Semiconductors
TDA8933B
Class D audio amplifier
8.2 Mode selection and interfacing
The TDA8933B can be switched to one of four operating modes using pins POWERUP and ENGAGE:
* Sleep mode: with low supply current. * Mute mode: the amplifiers are switching to idle (50 % duty cycle), but the audio signal
at the output is suppressed by disabling the Vl-converter input stages. The capacitors on pins HVP1 and HVP2 have been charged to half the supply voltage (asymmetrical supply only)
* Operating mode: the amplifiers are fully operational with an output signal * Fault mode
Both pins POWERUP and ENGAGE refer to pin CGND. Table 4 shows the different modes as a function of the voltages on the POWERUP and ENGAGE pins.
Table 4. Mode Sleep Mute Operating Fault
[1]
Mode selection for the TDA8933B Pin POWERUP[1] < 0.8 V 2 V to 6 V 2 V to 6 V 2 V to 6 V ENGAGE[1] < 0.8 V < 0.8 V 2.4 V to 6 V undefined DIAG undefined >2V >2V < 0.8 V
When there are symmetrical supply conditions, the voltage applied to pins POWERUP and ENGAGE must never exceed the supply voltage (VDDA, VDDP1 or VDDP2).
If the transition between Mute mode and Operating mode is controlled via a time constant, the start-up will be pop-free since the DC output offset voltage is applied gradually to the output. The bias current setting of the V/I-converters is related to the voltage on pin ENGAGE.
* Mute mode: the bias current setting of the V/I-converters is zero (V/I-converters
disabled).
* Operating mode: the bias current is at maximum.
The time constant required to apply the DC output offset voltage gradually between Mute mode and Operating mode can be generated by applying a capacitor on pin ENGAGE. The value of the capacitor on pin ENGAGE should be 470 nF.
TDA8933B_1
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Preliminary data sheet
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TDA8933B
Class D audio amplifier
VP
POWERUP
DREF OSCIO HVPREF
HVP1, HVP2 2.0 V (typical) 1.2 V (typical)
ENGAGE
0.8 V
OUT1, OUT2
AUDIO
AUDIO
AUDIO
PWM
PWM
PWM
DIAG
operating
mute
operating
fault
operating
sleep
010aaa457
Fig 3.
Start-up sequence
8.3 Pulse Width Modulation (PWM) frequency
The output signal of the amplifier is a PWM signal with a carrier frequency of approximately 320 kHz. Using a 2nd-order low-pass filter in the application results in an analog audio signal across the loudspeaker. The PWM switching frequency can be set by an external resistor Rosc connected between pin OSCREF and VSSD(HW). The carrier frequency can be set between 300 kHz and 500 kHz. Using an external resistor of 39 k, the carrier frequency is set to a typical value of 320 kHz (see Figure 4). If two or more TDA8933B devices are used in the same audio application, it is recommended to synchronize the switching frequency of all devices. See Section 14.6 for more information. The value of the resistor also sets the frequency of the carrier and can be calculated with Equation 1: 12.45x10 f osc = -----------------------R osc Where: fosc = oscillator frequency (Hz)
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(1)
Preliminary data sheet
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TDA8933B
Class D audio amplifier
Rosc = oscillator resistor () (on pin OSCREF)
010aaa531
550 fosc (kHz) 450
350
250 25 30 35 40 Rosc (k) 45
Fig 4.
Oscillation frequency as a function of Rosc
Table 5 summarizes how to configure the TDA8933B in master or slave configuration. For device synchronization see Section 14.6.
Table 5. Master or slave configuration Pin OSCREF Master Slave Rosc > 25 k to VSSD(HW) Rosc = 0 ; shorted to VSSD(HW) OSCIO output input
Configuration
8.4 Protections
The following protections are implemented in the TDA8933B:
* * * * *
Thermal Foldback (TF) OverTemperature Protection (OTP) OverCurrent Protection (OCP) Window Protection (WP) Supply voltage protections - UnderVoltage Protection (UVP) - OverVoltage Protection (OVP) - UnBalance Protection (UBP)
* Electro Static Discharge (ESD)
The behavior of the device under the different fault conditions differs according to the protection activated and is described in the following sections.
8.4.1 Thermal Foldback (FT)
If the junction temperature of the TDA8933B exceeds the threshold level (Tj > 140 C), the gain of the amplifier is decreased gradually to a level where the combination of dissipation (P) and the thermal resistance from junction to ambient (Rth(j-a)) results in a junction temperature of around the threshold level.
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Preliminary data sheet
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NXP Semiconductors
TDA8933B
Class D audio amplifier
This means that the device will not switch off completely, but remains operational at lower output power levels. With music output signals, this feature enables high peak output powers while still operating without any external heat sink other than the copper area on the Printed-Circuit Board (PCB). If the junction temperature still increases due to external causes the OTP shuts down the amplifier completely.
8.4.2 OverTemperature Protection (OTP)
If the junction temperature Tj > 155 C the power stage will shut down immediately.
8.4.3 OverCurrent Protection (OCP)
The OCP can distinguish between an impedance drop of the loudspeaker and a low-ohmic short circuit. If an impedance drop causes the output current to exceed 2 A, e.g. due to dynamic behavior of the loudspeaker, the amplifier will start limiting the current above 2 A. Therefore the current limiting feature will avoid audio interruption (audio holes) due to a loudspeaker impedance drop. If a fault condition causes the output current to exceed 2 A, like a short circuit between the loudspeaker terminals or from the loudspeaker terminal to the supply lines or ground, the amplifier is switched off and a timer of 100 ms is started. The DIAG is set low for the first 50 ms of the timer. The timer will keep the power stage disabled for at least 100 ms. Every 100 ms the amplifier will try to restart as long as the short circuit between the loudspeaker terminals remains. The average power dissipation in the TDA8933B will be low because the short circuit current will flow only during a very short time every 100 ms. If a short circuit occurs between a loudspeaker terminal and the supply lines or ground, the activated WP will keep the power stage disabled (no restart every 100 ms). Restart will take place after removing this short.
8.4.4 Window Protection (WP)
The window protection protects the amplifier against the following fault conditions:
* During the start-up sequence, when pin POWERUP is switched from Sleep mode to
Mute mode. In the event of a short circuit at one of the output terminals to VDDP1, VSSP1, VDDP2 or VSSP2 the start-up procedure is interrupted and the TDA8933B waits for open circuit outputs. Because the check is done before enabling the power stages no large currents will flow in the event of a short circuit.
* When the amplifier is shut down completely due to activation of the OCP or because
of a short circuit to one of the supply lines, then during restart (i.e. after 100 ms) the window protection will be activated. As a result the amplifier will not start up until the short circuit to the supply lines has been removed.
8.4.5 Supply voltage protection
If the supply voltage drops below 10 V the UnderVoltage Protection (UVP) circuit is activated and the system will shut down directly. This switch-off will be silent and without pop noise. When the supply voltage rises above the threshold level the power stage is restarted after 100 ms.
TDA8933B_1
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TDA8933B
Class D audio amplifier
If the supply voltage exceeds 36 V the OVP circuit is activated and the power stages will shut down. It is enabled again as soon as the supply voltage drops below the threshold level. The power stage is restarted after 100 ms. Supply voltages > 40 V may damage the TDA8933B. Two conditions should be distinguished here:
* If the supply voltage is pumped to higher values by the TDA8933B application itself
(see also Section 14.8), the OVP is triggered and the TDA8933B is shut down. The supply voltage will decrease and the TDA8933B is thus protected against any overstress.
* If a supply voltage > 40 V is caused by other or by external causes the TDA8933B will
shut down, but the device can still be damaged since the supply voltage in this case will remain > 40 V. The OVP protection is not a supply clamp. An additional UnBalance Protection (UBP) circuit compares the positive analog supply voltage VDDA with the negative analog supply voltage VSSA and is triggered if the difference between them exceeds a certain level. This level depends on the sum of both supply voltages. The UBP threshold levels can be defined as follows:
* LOW-level threshold: VP(th)(ubp)l < 8/5 x VHVPREF * HIGH-level threshold: VP(th)(ubp)h > 8/3 x VHVPREF
In a symmetrical supply the UBP is released when the unbalance of the supply voltage is within 6 % of its starting value. Table 6 shows an overview of all protections and their effect on the output signal.
Table 6. Protection OTP OCP WP UVP OVP UBP Overview of protections for the TDA8933B Restart When fault is removed no yes yes no no no Every 100 ms yes no no yes yes yes
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Preliminary data sheet
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TDA8933B
Class D audio amplifier
8.5 Diagnostic input and output
Except for TF, whenever one of the protections is triggered pin DIAG is activated to LOW level (see Table 6). An internal current source will pull up the open-drain DIAG output to approximately 2.5 V. This current source can deliver approximately 50 A. The DIAG pin refers to pin CGND. The diagnostic output signal during different short circuit conditions is illustrated in Figure 5. Using pin DIAG as input, a voltage < 0.8 V will put the device into Fault mode.
Vo 2.4 V
Vo 2.4 V
amplifier restart 0V 50 ms 50 ms shorted load 0V
no restart short to supply line
001aad759
Fig 5.
Diagnostic output for different short circuit conditions
8.6 Differential inputs
For a high common-mode rejection ratio and for maximum flexibility in the application the audio inputs are fully differential. By connecting the inputs anti-parallel the phase of one of the two channels can be inverted so that the amplifier can then operate as a mono BTL amplifier. The input configuration for a mono BTL application is illustrated in Figure 6. In the SE configuration it is also recommended to connect the two differential inputs in anti-phase. This has advantages for the current handling of the power supply at low signal frequencies and minimizes supply pumping (see also Section 14.8).
IN1P IN1N audio input
OUT1
IN2P IN2N
OUT2
001aad760
Fig 6.
Input configuration for a mono BTL application
TDA8933B_1
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TDA8933B
Class D audio amplifier
8.7 Output voltage buffers
When pin POWERUP is set HIGH the half-supply output voltage buffers are switched on in asymmetrical configuration. The start-up will then be pop-free because the device starts switching when the capacitor on pin HVPREF and the SE capacitors are completely charged. Output voltage buffer pins:
* Pins HVP1 and HVP2: The time required for charging the SE capacitor depends on its
value. The half-supply voltage output is disabled when the TDA8933B is used in a symmetrical supply application.
* Pin HVPREF: This output voltage reference buffer charges the capacitor on pin
HVPREF.
* Pin INREF: This output voltage reference buffer charges the input reference capacitor
on pin INREF, which applies the bias voltage for the inputs.
9. Internal circuitry
Table 7. Pin 1 16 17 32
VSSA 001aad784
Internal circuitry Symbol VSSD(HW)
1, 16, 17, 32 VDDA
Equivalent circuit
2 3 12 14 15
IN1P IN1N INREF IN2N IN2P
12
48 k 20 % 2 k 20 %
VDDA
2 k 20 %
2, 15
48 k 20 %
V/I
HVPREF
3, 14
V/I
VSSA
001aad785
TDA8933B_1
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TDA8933B
Class D audio amplifier
Internal circuitry Symbol DIAG
VDDA 2.5 V
50 A 500 20 %
Table 7. Pin 4
Equivalent circuit
4
100 k 20 %
VSSA
CGND
001aaf607
5
ENGAGE
VDDA 2.8 V
Iref = 50 A 2 k 20 %
5
100 k 20 %
VSSA
CGND
001aaf608
6
POWERUP
VDDA
6
VSSA
CGND
001aad788
7
CGND
VDDA
7
VSSA 001aad789
TDA8933B_1
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TDA8933B
Class D audio amplifier
Internal circuitry Symbol VDDA
8
Table 7. Pin 8
Equivalent circuit
VSSA
VSSD 001aad790
9
VSSA
VDDA
9
VSSD 001aad791
10
OSCREF
VDDA Iref 10
VSSA
001aad792
11
HVPREF
VDDA
11
VSSA
001aaf604
13
TEST
VDDA
13
VSSA 001aad795
TDA8933B_1
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TDA8933B
Class D audio amplifier
Internal circuitry Symbol DREF
VDD
Table 7. Pin 18
Equivalent circuit
18
VSSD 001aag025
19 30
HVP2 HVP1
VDDA
19, 30
VSSA
001aag026
20 23 26 29
VDDP2 VSSP2 VSSP1 VDDP1
23, 26
001aad798
20, 29
21 28
BOOT2 BOOT1
21, 28
OUT1, OUT2
001aad799
22 27
OUT2 OUT1
VDDP1, VDDP2
22, 27
VSSP1, VSSP2
001aag027
TDA8933B_1
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TDA8933B
Class D audio amplifier
Internal circuitry Symbol STAB2 STAB1
24, 25 VDDA
Table 7. Pin 24 25
Equivalent circuit
VSSP1, VSSP2
001aag028
31
OSCIO
DREF
31 VSSD 001aag029
10. Limiting values
Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VP Vx Parameter supply voltage voltage on pin x IN1P, IN1N, IN2P, IN2N OSCREF, OSCIO, TEST POWERUP, ENGAGE, DIAG all other pins IORM Tj Tstg Tamb P Vesd repetitive peak output current junction temperature storage temperature ambient temperature power dissipation electrostatic discharge voltage human body model machine model
[1] [2] [3] [4] [5] [6] [7]
TDA8933B_1
Conditions asymmetrical supply[1]
[2] [3] [4]
Min -0.3
Max +40.1
Unit V
-5 VSSD(HW) - 0.3 VCGND - 0.3 VSS - 0.3 2 -55 -40 -
+5 5 6
V V V
[5]
VDD + 0.3 V 150 +150 +85 5 +2000 +200 A C C C W V V
maximum output current limiting
[6]
[7]
-2000 -200
[8]
VP = VDDP1 - VSSP1 = VDDP2 - VSSP2 Measured with respect to pin INREF; Vx < VDD + 0.3 V. Measured with respect to pin VSSD(HW); Vx < VDD + 0.3 V. Measured with respect to pin CGND; Vx < VDD + 0.3 V. VSS = VSSP1 = VSSP2; VDD = VDDP1 = VDDP2. Current limiting concept. Human Body Model (HBM); Rs = 1500 ; C = 100 pF. For pins 2, 3, 11, 14 and 15 Vesd = 1800V.
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Class D audio amplifier
[8]
Machine Model (MM); Rs = 0 ; C = 200 pF; L = 0.75 H.
11. Thermal characteristics
Table 9. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions free air natural convection JEDEC test board Two-layer application board Three-layer application board j-lead thermal characterization parameter from junction to lead thermal characterization parameter from junction to top of package thermal resistance from junction to case free-air natural convection
[4] [1] [2] [3]
Min -
Typ 47 48 30 -
Max 50 30
Unit K/W K/W K/W K/W
j-top
-
-
2
K/W
Rth(j-c)
-
4.0
-
K/W
[1] [2] [3] [4]
Measured on a JEDEC high K-factor test board (standard EIA/JESO 51-7) in free air with natural convection. Measured on a two-layer application board (55 mm x 40 mm), 35 m copper, FR4 base material in free air with natural convection. Measured on a three-layer application board (70 mm x 50 mm), 35 m copper, FR4 base material in free air with natural convection. Strongly dependent on where the measurement is taken on the package.
12. Static characteristics
Table 10. Characteristics VP = 25 V, fosc = 320 kHz and Tamb = 25 C; unless specified otherwise. Symbol Supply VP IP Iq(tot) supply voltage supply current asymmetrical supply symmetrical supply Sleep mode total quiescent current Operating mode; no load, no snubbers or filter connected drain-source on-state resistance POWERUP[1] 0 VI = 3 V 0 2 1 6.0 20 0.8 6.0 V A V V Tj = 25 C Tj = 125 C 10 5 25 12.5 0.6 40 36 18 1.0 50 V V mA mA Parameter Conditions Min Typ Max Unit
Series resistance output switches RDSon 380 545 m m
Power-up input: pin VI II VIL VIH
input voltage input current LOW-level input voltage HIGH-level input voltage
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Class D audio amplifier
Table 10. Characteristics ...continued VP = 25 V, fosc = 320 kHz and Tamb = 25 C; unless specified otherwise. Symbol VO VI IO VIL VIH Parameter ENGAGE[1] 2.4 0 VI = 3 V 0 2.4 2.8 50 3.1 6.0 60 0.8 6.0 V V A V V output voltage input voltage output current LOW-level input voltage HIGH-level input voltage output voltage protection activated; see Table 6 Operating mode Bias voltage for inputs: pin INREF VO(bias) bias output voltage Reference to VSSA 2.1 V Half-supply voltage Pins HVP1 and HVP2 VO IO Pin HVPREF VO output voltage half-supply reference voltage in Mute mode reference to VSSA SE; with respect to HVPREF Mute mode Operating mode BTL Mute mode Operating mode Stabilizer output: pins STAB1, STAB2 VO output voltage Mute mode and Operating mode; with respect to pins VSSP1 and VSSP2 10 11 12 V 20 150 mV mV 15 100 mV mV 0.5VP - 0.2 V 0.5VP 0.5VP + 0.2 V V output voltage output current half-supply voltage to charge SE capacitor VHVP1 = VHVP2 = VO - 1 V 0.5VP - 0.2 V 0.5VP 50 0.5VP + 0.2 V V mA Conditions Min Typ Max Unit Engage input: pin
Diagnostic output: pin DIAG[1] VO 2 2.5 0.8 3.3 V V
Reference voltage for internal logic: pin DREF VO VO(offset) output voltage output offset voltage 4.5 4.8 5.1 V Amplifier outputs: pins OUT1 and OUT2
Voltage protections VP(uvp) undervoltage protection supply voltage overvoltage protection supply voltage 8.0 9.5 9.9 V
VP(ovp)
36.1
38.5
40
V
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Class D audio amplifier
Table 10. Characteristics ...continued VP = 25 V, fosc = 320 kHz and Tamb = 25 C; unless specified otherwise. Symbol VP(th)(ubp)l Parameter low unbalance protection threshold supply voltage high unbalance protection threshold supply voltage overcurrent protection output current thermal protection activation temperature thermal foldback activation temperature HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage maximum number of slaves driven by one master Conditions VP = 22 V; VHVPREF = 11 V VP = 22 V; VHVPREF = 11 V Min Typ Max 18 Unit V
VP(th)(ubp)h
29
-
-
V
Current protections IO(ocp) current limiting 2.0 2.5 A
Temperature protection Tact(th_prot) Tact(th_fold) 155 140 160 150 C C
Oscillator reference: pin OSCIO[2] VIH VIL VOH VOL Nslave(max) 4.0 0 4.0 0 12 5.0 0.8 5.0 0.8 V V V V -
[1] [2]
Measured with respect to pin CGND. Measured with respect to pin VSSD(HW).
13. Dynamic characteristics
Table 11. Switching characteristics VP = 25 V; Tamb = 25 C; unless otherwise specified. Symbol fosc Parameter oscillator frequency Conditions Rosc = 39 k range Timing PWM output: pins OUT1 and OUT2 tr tf tw(min) rise time fall time minimum pulse width IO = 0 A IO = 0 A IO = 0 A 10 10 80 ns ns ns Min 300 Typ 320 Max 500 Unit kHz kHz Internal oscillator
TDA8933B_1
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Preliminary data sheet
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NXP Semiconductors
TDA8933B
Class D audio amplifier
Table 12. SE characteristics VP = 25 V, RL = 2 x 8 , fi = 1 kHz, fosc = 320 kHz, RS < 0.1 [1] and Tamb = 25 C; unless otherwise specified. Symbol Po(RMS) Parameter RMS output power Conditions continuous time output power per RL = 4 ; VP = 17 V THD+N = 0.5 %, fi = 1 kHz THD+N = 0.5 %, fi = 100 Hz THD+N = 10 %, fi = 1 kHz THD+N = 10 %, fi = 100 Hz RL = 8 ; VP = 25 V THD+N = 0.5 %, fi = 1 kHz THD+N = 0.5 %, fi = 100 Hz THD+N = 10 %, fi = 1 kHz THD+N = 10 %, fi = 100 Hz THD+N total harmonic distortion-plus-noise Po = 1 W fi = 1 kHz fi = 6 kHz Gv(cl) |GV| cs SVRR closed-loop voltage gain voltage gain difference channel separation supply voltage ripple rejection Po = 1 W; fi = 1 kHz Operating mode fi = 100 Hz fi = 1 kHz |Zi| Vn(o) VO(mute) CMRR po input impedance output noise voltage mute output voltage common mode rejection ratio output power efficiency differential Operating mode; Ri = 0 Mute mode Mute mode; Vi = 1 V (RMS) Vi(cm) = 1 V (RMS) VP = 17 V; RL = 4 ; Po = 8 W/channel VP = 25 V; RL = 8 ; Po = 10 W/channel
[1] [2] [3] [4] [5]
[5] [5] [4] [3]
Min channel[2] 5.9 7.5 7.3 9.3 29 70 40 70 86 89
Typ
Max
Unit
6.8 6.8 8.5 8.5 8.2 8.2 10.3 10.3 0.014 0.05 30 0.5 80 60 50 100 100 70 100 75 89 92
0.1 0.1 31 1 150 100 -
W W W W W W W W % % dB dB dB dB dB k V V V dB % %
Vi =100 mV; no load
RS is the total series resistance of an inductor and a ESR single ended capacitor in the application. Output power is measured indirectly; based on RDSon measurement. THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall. Vripple = 2 V (p-p); Ri = 0 . B = 20 Hz to 20 kHz, AES17 brick wall.
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NXP Semiconductors
TDA8933B
Class D audio amplifier
Table 13. BTL characteristics VP = 25 V, RL = 16 , fi = 1 kHz, fosc = 320 kHz, RS < 0.1 [1] and Tamb = 25 C; unless otherwise specified. Symbol Po(RMS) Parameter RMS output power Conditions continuous time output RL = 8 ; VP = 17 V THD+N = 0.5 %, fi = 1 kHz THD+N = 0.5 %, fi = 100 Hz THD+N = 10 %, fi = 1 kHz THD+N = 10 %, fi = 100 Hz RL = 16 ; VP = 25 V THD+N = 0.5 %, fi = 1 kHz THD+N = 0.5 %, fi = 100 Hz THD+N = 10 %, fi = 1 kHz THD+N = 10 %, fi = 100 Hz THD+N total harmonic distortion-plus-noise Po = 1 W fi = 1 kHz fi = 6 kHz Gv(cl) |Zi| Vn(o) closed-loop voltage gain input impedance output noise voltage differential Ri = 0 Operating mode Mute mode VO(mute) CMRR po mute output voltage common mode rejection ratio output power efficiency Mute mode; Vi = 1 V (RMS) Vi(cm) = 1 V (RMS) Po = 17 W; VP = 17 V; RL = 8 Po = 21 W; VP = 25 V; RL = 16
[1] [2] [3] [4] [5]
[5] [4] [4] [3]
Min power[2] 11.9 15.4 14.9 18.9 35 35 89 92
Typ
Max
Unit
13.7 13.7 17.1 17.1 16.5 16.5 20.6 20.6 0.01 0.04 36 50 100 70 100 75 91 94
0.1 0.1 37 150 100 -
W W W W W W W W % % dB k V V V dB % %
RS is the total series resistance of an inductor and a ESR single ended capacitor in the application. Output power is measured indirectly; based on RDSon measurement. THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall. B = 22 Hz to 20 kHz, AES17 brick wall.
2 Po po = ---------------------2 Po + P
14. Application information
14.1 Output power estimation
The output power Po at THD+N = 0.5 %, just before clipping, for the SE and the BTL configurations can be estimated using Equation 2 and Equation 3.
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Preliminary data sheet
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TDA8933B
Class D audio amplifier
SE configuration:
2 RL ---------------------------------------------------------- x ( 1 - t x f osc ) x V P w ( min ) R L + R DSon + R s + R ESR = -----------------------------------------------------------------------------------------------------------------------------------------8 x RL
P o ( 0.5% )
(2)
BTL configuration:
2 RL ------------------------------------------------------ x ( 1 - t - w ( min ) x f osc ) x V P R L + 2 x ( R DSon + R s ) = -------------------------------------------------------------------------------------------------------------------------------------2 x RL
P o ( 0.5% ) Where:
(3)
* * * * * * *
VP = supply voltage VDDP1 - VSSP1 (V) or VDDP2 - VSSP2 (V) RL = load resistance () RDSon = drain-source on-state resistance () Rs = series resistance output inductor () RESR = Equivalent Series Resistance SE capacitance () tw(min) = minimum pulse width(s); 80 ns typical fosc = oscillator frequency (Hz); 320 kHz typical with Rosc = 39 k
The output power Po at THD+N = 10 % can be estimated by: P o ( 10% ) = 1.25 x P o ( 0.5% ) Figure 7 and Figure 8 show the estimated output power at THD+N = 0.5 % and THD+N = 10 % as a function of the supply voltage for SE and BTL configurations at different load impedances. The output power is calculated with: RDSon = 0.38 (at Tj = 25 C), Rs = 0.05 , RESR = 0.05 and IO(ocp) = 2 A (minimum). (4)
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NXP Semiconductors
TDA8933B
Class D audio amplifier
20 Po (0.5 %) (W/channel) 16
010aaa499
20 Po (10 %) (W/channel)
010aaa500
(3)
(3)
16
(2)
12
(2)
12
(1)
8
(1)
8
4
4
0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V)
0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V)
a. THD+N = 0.5 %
(1) RL = 4 (2) RL = 6 (3) RL = 8
b. THD+N = 10 %
When the maximum current of 2 A is reached, the current limitation feature becomes active. See also Section 8.4.3 for OCP details.
Fig 7.
SE output power as a function of supply voltage
40 Po (0.5 %) (W)
010aaa501
40 Po (10 %) (W)
010aaa502
(3)
(3)
30
30
20
(2) (1)
20
(1)
(2)
10
10
0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V)
0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V)
a. THD+N = 0.5 %
(1) RL = 6 (2) RL = 8 (3) RL = 16
b. THD+N = 10 %
When the maximum current of 2 A is reached, the current limitation feature becomes active. See also Section 8.4.3 for OCP details.
Fig 8.
BTL output power as a function of supply voltage
TDA8933B_1
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NXP Semiconductors
TDA8933B
Class D audio amplifier
14.2 Output current limitation
The peak output current IO(max) is internally limited to a minimum value of 2 A. During normal operation the output current should not exceed this threshold level, otherwise the signal will be distorted. The peak output current in SE or BTL configurations can be calculated using Equation 5 and Equation 6. SE configuration: 0.5 x V P I O ( max ) ---------------------------------------------------------- 2 A R L + R DSon + R s + R ESR BTL configuration: VP I O ( max ) ----------------------------------------------------- 2 A R L + 2 x ( R DSon + R s ) Where: (6) (5)
* * * * *
VP = supply voltage VDDP1 - VSSP1 (V) or VDDP2 - VSSP2 (V) RL = load resistance () RDSon = drain-source on-state resistance () Rs = series resistance output inductor () RESR = Equivalent Series Resistance SE capacitance ()
Example: An 8 speaker in the BTL configuration can be used up to a supply voltage of 18 V without running into current limiting. Current limiting (clipping) will avoid audio holes but produces a similar distortion to voltage clipping.
14.3 Speaker configuration and impedance
For a flat frequency response (second-order Butterworth filter with an output frequency of 40 kHz) it is necessary to change the low-pass filter components LLC and CLC according to the speaker configuration and impedance. Table 14 shows the values required in practice.
Table 14. SE Filter component values RL () 4 6 8 BTL 8 16 LLC (H) 22 33 47 22 47 CLC (nF) 680 470 330 680 330
Configuration
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NXP Semiconductors
TDA8933B
Class D audio amplifier
14.4 Single-ended capacitor
The SE capacitor forms a high-pass filter with the speaker impedance. This means that the frequency response will roll off with 20 dB per decade below f-3dB and a cut-off frequency of 3 dB. The 3 dB cut-off frequency is equal to: 1 f -3dB = ---------------------------------2 x R L x C SE Where: (7)
* f-3dB = 3 dB cut-off frequency (Hz) * RL = load resistance (W) * CSE = single-ended capacitance (F); see Figure 32
Table 15 shows an overview of the required SE capacitor values in the case of a 60 Hz, 40 Hz or 20 Hz 3 dB cut-off frequency.
Table 15. SE capacitor values CSE (F) f-3dB = 60 Hz 4 6 8 680 470 330 f-3dB = 40 Hz 1000 680 470 f-3dB = 20 Hz 2200 1500 1000
Impedance ()
14.5 Gain reduction
The gain of the TDA8933B is internally fixed at 30 dB for SE and 36 dB for BTL. The gain can be reduced by a resistive voltage divider at the input (see Figure 9).
R1
470 nF R3 100 k
audio in
R2 470 nF
010aaa137
Fig 9.
Input configuration for reducing gain
When applying a resistive divider, the total voltage gain Gv(tot) can be calculated using Equation 8 and Equation 9: R EQ G v ( tot ) = G v ( cl ) + 20 log ----------------------------------------R EQ + ( R1 + R2 ) Where: (8)
* Gv(tot) = total voltage gain (dB) * Gv(cl) = closed-loop voltage gain, fixed at 30 dB for SE (dB) * REQ = equivalent resistance, R3 and Zi ()
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NXP Semiconductors
TDA8933B
Class D audio amplifier
* R1 = series resistors () * R2 = series resistors ()
R3 x Z R EQ = -----------------i R3 + Z i Where: (9)
* REQ = equivalent resistance () * R3 = parallel resistor () * Zi = internal input impedance ()
Example: Substituting R1 = R2 = 4.7 k, Zi = 100 k and R3 = 22 k in Equation 8 and Equation 9 results in a gain of Gv(tot) = 26.3 dB.
14.6 Device synchronization
If two or more TDA8933B devices are used in one application it is recommended that all the devices are synchronized at the same switching frequency to avoid beat tones. This can be done by connecting all OSCIO pins together and configuring one of the devices as master while the others are configured as slaves (see Figure 10). A device is configured as master when a resistor Rosc is connected between pin OSCREF and pin VSSD(HW), thus setting the carrier frequency. Pin OSCIO of the master is then configured as an oscillator output for synchronization. The OSCREF pins of the slave devices should be shorted to pin VSSD(HW), configuring pin OSCIO as an input.
master IC1 slave IC2
TDA8933B
OSCREF VSSD(HW) OSCIO
TDA8933B
OSCIO VSSD(HW) OSCREF
Cosc 100 nF
Rosc 39 k
010aaa138
Fig 10. Master/slave concept in a two-chip application
TDA8933B_1
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NXP Semiconductors
TDA8933B
Class D audio amplifier
14.7 Thermal behavior (PCB considerations)
The TDA8933B is available in a thermally enhanced HTSSOP32 (SOT549-1) package for reflow soldering. The HTSSOP32 package has an exposed die pad that reduces significantly the overall Rth(j-a). Therefore it is required to solder the exposed die pad (at VSSD level) to a copper plane for cooling. A low thermal-resistance can be achieved when using a multilayer PCB with sufficient space for two or three thermal planes. Increasing the area of the thermal plane, the number of planes or the copper thickness can reduce further the thermal resistance Rth(j-a) of both packages. Find below the typical thermal resistance (free air and natural convection) of two practical PCB implementations:
* Rth(j-a) = 48 K/W for a small two-layer application board (55 mm x 40 mm, m copper,
FR4 base material).
* Rth(j-a) = 30 K/W for a three-layer application board (70 mm x 50 mm, 35 m copper,
FR4 base material). Equation 10 shows the relation between the maximum allowable power dissipation P and the thermal resistance from junction to ambient. T j ( max ) - T amb R th ( j - a ) = ----------------------------------P Where: (10)
* * * *
Rth(j-a) = thermal resistance from junction to ambient (K/W) Tj(max) = maximum junction temperature (C) Tamb = ambient temperature (C) P = power dissipation, which is determined by the efficiency of the TDA8933B
The power dissipation is shown in Figure 19 (SE) and Figure 27 (BTL). Thermal foldback will limit the maximum junction temperature to 140 C.
14.8 Pumping effects
When the amplifier is used in an SE configuration a so-called `pumping effect' can occur. During one switching interval, energy is taken from one supply (e.g. VDDP1), while a part of that energy is delivered back to the other supply line (e.g. VSSP1) and vice versa. When the power supply cannot sink energy the voltage across output capacitors that power supply will increase. The voltage increase caused by the pumping effect depends on:
* * * * *
TDA8933B_1
Speaker impedance Supply voltage Audio signal frequency Value of decoupling capacitors on supply lines Source and sink currents of other channels
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NXP Semiconductors
TDA8933B
Class D audio amplifier
The pumping effect should not cause a malfunction of either the audio amplifier or the power supply, which can also be caused by triggering of the undervoltage or overvoltage protection of the amplifier. Pumping effects in an SE configuration can be minimized by connecting audio inputs in anti-phase and changing the polarity of one speaker as shown in Figure 11.
IN1P audio in1 OUT1 IN1N
IN2N audio in2 OUT2 IN2P
010aaa140
Fig 11. SE application for reducing pumping effect
14.9 SE curves measured in the reference design
102 THD+N (%) 10
010aaa503
102 THD+N (%) 10
010aaa504
1
1
10-1
(3) (1)
10-1
(1)
(3)
(2)
10-2
(2)
10-2
10-3 10-2
10-1
1
10 102 Po (W/channel)
10-3 10-2
10-1
1
10 102 Po (W/channel)
a. VP = 25 V; RL = 2 x 8 SE
(1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz
b. VP = 17 V; RL = 2 x 4 SE
Fig 12. Total harmonic distortion-plus-noise as a function of output power
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NXP Semiconductors
TDA8933B
Class D audio amplifier
102 THD+N (%) 10
010aaa505
102 THD+N (%) 10
010aaa506
1
1
10-1
(1)
10-1
(1)
(2)
10-2
(2)
10-2
10-3 10
102
103
104
fi (Hz)
105
10-3 10
102
103
104
fi (Hz)
105
a. VP = 25 V; RL = 2 x 8 SE
(1) Po = 7 W (2) Po = 1 W
b. VP = 17 V; RL = 2 x 4 SE
Fig 13. Total harmonic distortion-plus-noise as a function of frequency
40 Gv(cl) (dB) 30
(2)
010aaa507
0 SVRR (dB) -20
010aaa508
-40
(1)
20
(2)
-60 (1)
10 10
102
103
104
fi (Hz)
105
-80 10
102
103
104
fi (Hz)
105
Ri = 0 ; Vi = 100 mV (RMS); Cse = 1000 F (1) RL = 2 x 4 SE at VP = 17 V (2) RL = 2 x 8 SE at VP = 25 V
Vripple = 500 mV (RMS) referenced to ground; Shorted input; CHVPREF = 47 F (1) VP = 17 V; RL = 2 x 4 SE (2) VP = 25 V; RL = 2 x 8 SE
Fig 14. Gain as a function of frequency
Fig 15. Supply voltage ripple rejection as a function of frequency
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Preliminary data sheet
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NXP Semiconductors
TDA8933B
Class D audio amplifier
100 S/N (dB) 80
(1) (2)
010aaa509
0 cs (dB) -20
010aaa510
60
-40
40
-60
(1)
20
-80
(2)
0 10-2
10-1
1
10
Po (W)
102
-100 10
102
103
104
fi (Hz)
105
Ri = 0 ; 20 kHz brick wall filter AES17 (1) RL = 2 x 4 SE at VP = 17 V (2) RL = 2 x 8 SE at VP = 25 V
Po = 1 W (1) RL = 2 x 4 SE at VP = 17 V (2) RL = 2 x 8 SE at VP = 25 V
Fig 16. Signal-to-noise ratio as a function of output power
Fig 17. Channel separation as a function of frequency
100 po (%) 80
(1) (2)
010aaa511
3.0 P (W) 2.0
010aaa512
60
(1) (2)
40 1.0 20
0 0 3 6 9 12 15 Po (W/channel)
0.0 10-2
10-1
1
10 102 Po (W/channel)
fi = 1 kHz; po = -----------------------(1) RL = 2 x 4 SE at 17 V (2) RL = 2 x 8 SE at 25 V
2 x Po 2 x Po + P
fi = 1 kHz; Power dissipation in junction only (1) RL = 2 x 4 SE at 17 V (2) RL = 2 x 8 SE at 25 V
Fig 18. Output power efficiency as a function of output power
Fig 19. Power dissipation as a function of output power per channel (two channels driven)
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NXP Semiconductors
TDA8933B
Class D audio amplifier
30 Po (W/channel)
010aaa513
4.0 P (W)
010aaa514
(1)
3.0
(1)
(2)
20
(2)
2.0
10
(3) (4)
1.0
0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V)
0.0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V)
fi = 1 kHz; Short time Po (1) RL = 2 x 8 SE at THD = 10 % (2) RL = 2 x 8 SE at THD = 0.5 % (3) RL = 2 x 4 SE at THD = 10 % (4) RL = 2 x 4 SE at THD = 0.5 %
fi = 1 kHz; Po at THD+N = 10 %; Power dissipation in junction only (1) RL = 2 x 4 SE (2) RL = 2 x 8 SE
Fig 20. Maximum output power per channel as a function of supply voltage
Fig 21. Power dissipation as a function of supply voltage
4 Vo (V) 3 Operating
010aaa515
4 Vo (V) 3
010aaa516
Operating
2
2
1
1
Sleep 0 0 0.5 1 1.5 2 2.5 3 VPOWERUP (V) 0 0
Mute 0.5 1.0 1.5 2.0 2.5 3.0 VENGAGE (V)
VENGAGE > 2 V; fi = 1 kHz; Vi = 100 mV (RMS)
VPOWERUP = 2 V; fi = 1 kHz; Vi = 100 mV (RMS)
Fig 22. Output voltage as a function of voltage on pin POWERUP
Fig 23. Output voltage as a function of voltage on pin ENGAGE
TDA8933B_1
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NXP Semiconductors
TDA8933B
Class D audio amplifier
14.10 BTL curves measured in the reference design
102 THD+N (%) 10
010aaa517
102 THD+N (%) 10
010aaa518
1
1
10-1
(1)
10-1
(1)
10-2
(2)
10-2
(2)
(3) (3)
10-3
10-2
10-1
1
10
Po (W)
102
10-3 10-2
10-1
1
10
Po (W)
102
a. VP = 17 V; RL = 8 BTL
(1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 1 kHz
b. VP = 25 V; RL = 16 BTL
Fig 24. Total harmonic distortion-plus-noise as a function of output power
102 THD+N (%) 10
010aaa519
102 THD+N (%) 10
010aaa520
1
1
10-1
(1)
10-1
(1)
10-2
10-2
(2)
(2)
10-3 10
102
103
104
fi (Hz)
105
10-3 10
102
103
104
fi (Hz)
105
a. VP = 17 V; RL = 8 BTL
(1) Po = 12 W (2) Po = 1 W
b. VP = 25 V; RL = 16 BTL
(1) Po = 10 W (2) Po = 1 W
Fig 25. Total harmonic distortion-plus-noise as a function of frequency
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Preliminary data sheet
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NXP Semiconductors
TDA8933B
Class D audio amplifier
100 po (%) 80
010aaa521
(2) (1)
45 Gv(cl) (dB) 35
010aaa522
(1) (2)
60
40 25 20
0 0 5 10 15 20 Po (W) 25
15 10
102
103
104
fi (Hz)
105
fi = 1 kHz (1) 8 BTL at 17 V (2) 16 BTL at 25 V
Vi = 100 mV (RMS) (1) RL = 8 BTL at VP = 17 V (2) RL = 16 BTL at VP = 25 V
Fig 26. Output power efficiency as a function of output power
Fig 27. Gain as a function of frequency
3 P (W) 2
010aaa523
5 P (W) 4
010aaa524
(1)
3
(2)
(1)
2
(2)
1 1
0 10-2
10-1
1
10
Po (W)
102
0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V)
fi = 1 kHz; Power dissipation in junction only (1) 8 BTL at 17 V (2) 16 BTL at 25 V
fi = 1 kHz; Po at THD+N = 10 %; Power dissipation in junction only (1) RL = 8 BTL (2) RL = 16 BTL
Fig 28. Power dissipation as a function of output power
Fig 29. Power dissipation as a function of supply voltage
TDA8933B_1
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Preliminary data sheet
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NXP Semiconductors
TDA8933B
Class D audio amplifier
50 Po (W) 40
010aaa525
0 SVRR (dB) -20
010aaa526
(1)
(2)
30
(3)
-40
20
(4)
-60
(1)
10
-80
(2)
0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V)
-100 10
102
103
104
fi (Hz)
105
fi = 1 kHz (1) 16 BTL at THD+N = 10 % (2) 16 BTL at THD+N = 0.5 % (3) 8 BTL at THD+N = 10 % (4) 8 BTL at THD+N = 0.5 %
Vripple = 500 mV (RMS) with relation to ground; Shorted inputs; CHVP = 100 nF (1) VP = 17 V; RL = 8 BTL (2) VP = 25 V; RL = 16 BTL
Fig 30. Output power as a function of supply voltage
Fig 31. Supply voltage ripple rejection as a function of frequency
TDA8933B_1
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Preliminary data sheet
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NXP Semiconductors
TDA8933B
Class D audio amplifier
14.11 Typical application schematics (simplified)
VP
Rvdda
VP
10
VPA
Cvdda 100 nF Cvddp 220 F (35 V)
GND
VSSD(HW)
Cin 470 nF Cin 470 nF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1 STAB1 STAB2 VSSP2 OUT2 BOOT2 VDDP2 HVP2 DREF VSSD(HW)
Cdref 100 nF Cbo 15 nF Optional Cstab 100 nF Rsn 10 Csn 470 pF Clc Cse Cbo 15 nF
IN1P IN1N DIAG ENGAGE
Cen 470 nF
VP
Cvddp 100 nF Llc
MUTE control
POWERUP CGND
SLEEP control
Cosc 100 nF Rosc 39 k Chvpref 47 F (25 V) Cinref 100 nF Cin 470 nF Cin 470 nF
VPA
VDDA VSSA OSCREF HVPREF INREF TEST IN2N IN2P VSSD(HW)
U1 TDA8932B
25 24 23 22 21 20 19 18 17
Optional
Llc
Rsn 10 Csn 470 pF Clc Cse
VP Cvddp 100 nF
010aaa527
Fig 32. Typical simplified application diagram for 2 x SE (asymmetrical supply)
TDA8933B_1
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NXP Semiconductors
TDA8933B
Class D audio amplifier
VP
Rvdda
VP
10
VPA
Cvdda 100 nF Cvddp 220 F (35 V)
GND
VSSD(HW)
Cin Cin 1 F 1 F
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1 STAB1
Rsn 10 Csn 470 pF Cstab 100 nF Clc Cbo 15 nF Rhvp 470 Rhvp 470
IN1P IN1N DIAG MUTE control SLEEP control
Cosc 100 nF Rosc 39 k
VP
Cvddp 100 nF Llc Chvp 100 nF
ENGAGE
Cen 470 nF
POWERUP CGND VPA VDDA VSSA OSCREF HVPREF INREF
25 U1 TDA8932B STAB2 24 23 22 21 20 19 18 17 VSSP2 OUT2 BOOT2 VDDP2 HVP2 DREF VSSD(HW)
Cdref 100 nF Cbo 15 nF
Optional
Llc
Clc
Chvp 100 nF
Cinref 100 nF
TEST IN2N IN2P
Rsn 10
VP Cvddp 100 nF
Optional
Csn 470 pF
VSSD(HW)
Chvp 100 nF
010aaa528
Fig 33. Typical simplified application diagram for 1 x BTL (asymmetrical supply)
TDA8933B_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 23 October 2008
36 of 42
NXP Semiconductors
TDA8933B
Class D audio amplifier
VDD
Rvdda
VDD
10
VDDA
Cvdda 100 nF Cvddp 220 F (25 V) Cvssp 220 F (25 V)
GND
Rvssa Cvssa 100 nF
VSS
10
VSSA VSS
Cin 470 nF Cin
VSSD(HW) VSSA 1 IN1P IN1N DIAG ENGAGE
Cen 470 nF
32 31 30 29 28 27 26
VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1 STAB1
Cstab 100 nF Cbo 15 nF
VSSA
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
470 nF
VDD
Cvddp 100 nF Llc
MUTE control
POWERUP CGND
SLEEP control
Cosc 100 nF Rosc 39 k
Optional VSS
Cvssp 100 nF
VDDA VSSA
VDDA VSSA OSCREF HVPREF INREF
Rsn 10 Csn 470 pF Clc
25 U1 TDA8932B STAB2 24 23 22 21 20 19 18 17 VSSP2 OUT2 BOOT2 VDDP2 HVP2 DREF VSSD(HW)
Cdref 100 nF Cbo 15 nF
VSS
Cvssp 100 nF Llc
VSSA
Optional
Rsn 10 Csn 470 pF Clc
Cinref 100 nF Cin 470 nF Cin 470 nF
TEST VSSA IN2N IN2P VSSA VSSD(HW)
VDD Cvddp 100 nF
VSSA
010aaa529
Fig 34. Typical simplified application diagram for 2 x SE (symmetrical supply)
TDA8933B_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 23 October 2008
37 of 42
NXP Semiconductors
TDA8933B
Class D audio amplifier
VDD
Rvdda
VDD
10
VDDA
Cvdda 100 nF Cvddp 220 F (25 V) Cvssp 220 F (25 V)
GND
Rvssa Cvssa 100 nF
VSS
10
VSSA VSS
VSSA
Cin Cin 1 F 1 F
VSSD(HW) IN1P IN1N DIAG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1 STAB1
Cbo 15 nF
VSSA
VDD
Cvddp 100 nF Llc
MUTE control SLEEP control
ENGAGE
Cen 470 nF
POWERUP CGND
Optional VSS
Cvssp 100 nF Cstab 100 nF
Cosc 100 nF Rosc
VDDA VSSA
VDDA VSSA OSCREF HVPREF INREF
Rsn 10 Csn 470 pF
Clc
25 U1 TDA8932B STAB2 24 23 22 21 20 19 18 17 VSSP2 OUT2 BOOT2 VDDP2 HVP2 DREF VSSD(HW)
Cdref 100 nF Cbo 15 nF
VSS
Cvssp 100 nF
VSSA
39 k
Clc Llc
Cinref 100 nF
TEST VSSA IN2N IN2P VSSA VSSD(HW)
VDD
Cvddp 100 nF
Rsn 10
Optional
Csn 470 pF
VSSA
010aaa530
Fig 35. Typical simplified application diagram for 1 x BTL (symmetrical supply)
TDA8933B_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 23 October 2008
38 of 42
NXP Semiconductors
TDA8933B
Class D audio amplifier
15. Package outline
HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-1
D
E
A X
c y exposed die pad side HE vMA
Z
Dh
32
17
Eh pin 1 index
A2 A1
(A3)
A
Lp L
1
e bp
16
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.09 D(1) 11.1 10.9 Dh 5.1 4.9 E(2) 6.2 6.0 Eh 3.6 3.4 e 0.65 HE 8.3 7.9 L 1 Lp 0.75 0.50 v 0.2 w 0.1 y 0.1 Z 0.78 0.48
8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT549-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-04-07 05-11-02
Fig 36. Package outline SOT549-1 (HTSSOP32)
TDA8933B_1 (c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 23 October 2008
39 of 42
NXP Semiconductors
TDA8933B
Class D audio amplifier
16. Revision history
Table 16. Revision history Release date 20081023 Data sheet status Preliminary data sheet Change notice Supersedes Document ID TDA8933B_1
TDA8933B_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 23 October 2008
40 of 42
NXP Semiconductors
TDA8933B
Class D audio amplifier
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA8933B_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 23 October 2008
41 of 42
NXP Semiconductors
TDA8933B
Class D audio amplifier
19. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.6 8.7 9 10 11 12 13 14 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.11 15 16 17 17.1 17.2 17.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Mode selection and interfacing . . . . . . . . . . . . . 6 Pulse Width Modulation (PWM) frequency . . . . 7 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Foldback (FT) . . . . . . . . . . . . . . . . . . . 8 OverTemperature Protection (OTP) . . . . . . . . . 9 OverCurrent Protection (OCP) . . . . . . . . . . . . . 9 Window Protection (WP). . . . . . . . . . . . . . . . . . 9 Supply voltage protection . . . . . . . . . . . . . . . . . 9 Diagnostic input and output . . . . . . . . . . . . . . 11 Differential inputs . . . . . . . . . . . . . . . . . . . . . . 11 Output voltage buffers. . . . . . . . . . . . . . . . . . . 12 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal characteristics. . . . . . . . . . . . . . . . . . 17 Static characteristics. . . . . . . . . . . . . . . . . . . . 17 Dynamic characteristics . . . . . . . . . . . . . . . . . 19 Application information. . . . . . . . . . . . . . . . . . 21 Output power estimation. . . . . . . . . . . . . . . . . 21 Output current limitation . . . . . . . . . . . . . . . . . 24 Speaker configuration and impedance . . . . . . 24 Single-ended capacitor . . . . . . . . . . . . . . . . . . 25 Gain reduction . . . . . . . . . . . . . . . . . . . . . . . . 25 Device synchronization . . . . . . . . . . . . . . . . . . 26 Thermal behavior (PCB considerations). . . . . 27 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 27 SE curves measured in the reference design. 28 BTL curves measured in the reference design 32 Typical application schematics (simplified) . . . 35 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 40 Legal information. . . . . . . . . . . . . . . . . . . . . . . 41 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 17.4 18 19 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Contact information . . . . . . . . . . . . . . . . . . . . 41 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 October 2008 Document identifier: TDA8933B_1

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